The present invention is related to the use of a digital emulator circuit to speed the design of mixed digital/analog signal integrated circuits and in particular, the design of such integrated circuits with RF (Radio Frequency) signal components.
Many of the advances in the present revolution in telecommunications have come in the field of wireless communications. In wireless communication systems, the broadcast signals are RF, and in many of such communication systems the signals are processed in digital form. Until now, the components handling these disparate types of signals were separate analog and digital devices. However, with the demand for handheld devices, such as telephones, pagers and personal digital assistants (PDAs), many of these analog and digital circuit components are being integrated on a single chip to achieve low power, lower costs, and miniaturization.
However, there are problems with the association of digital and analog circuits on a single integrated circuit. For example, the high-speed switching in the digital circuit portion of the integrated circuit creates noise that can adversely affect the circuits in the analog portion of the integrated circuit. There are radiative and both capacitive as well as conductive coupling components of noise generated by the digital circuits that interfere with sensitive circuits in the analog circuit portion.
Because of these noise sources, proper and timely evaluation of the analog portion during product development requires that the digital portion function correctly and be ready for integration at the same time as the analog portion. Unfortunately, with existing design methodologies, this is not often possible. The design of the digital portion may be delayed, therefore postponing analog evaluation. This may occur in part because different designers, design groups, or even companies are working on each portion. Also, early versions of the digital portion may not work properly, and therefore will not generate the same noise as later corrected versions. This complicates the analog designer's task since as the noise profile of the digital portion changes, so does the analog portion's response.
Furthermore, there are usually several ways to design the architecture of a digital portion. Each of these will have a different noise profile, so the analog circuits will respond differently. While a particular architecture's noise may have a comparatively benign profile, this is very difficult to discover since it would involve the design and manufacture of a new chip for each architecture that a designer wants to try.